This invention relates to a novel masking method for masking necessary parts of a surface of a semiconductor substrate by using resists and oblique irradiation of the surface and a method of manufacturing semiconductor devices by using the masking method.
There are a variety of semiconductor devices manufactured by selective diffusion or selective ion implantation. In a conventional selective diffusion or selective ion implantation technique, the surface of a semiconductor is coated with photo resist, and the portions thereof corresponding to windows are removed. In addition, the semiconductor oxide film exposed in the windows is removed by using an etching liquid to form a mask, and impurity diffusion or ion implantation is effected through the windows, thereby to form semiconductor regions having desired conduction types. However, in the case of forming one unitary semiconductor element, this mask formation process must be repeated several times. For instance, in manufacturing a bipolar IC, one mask is necessary for each of the buried layer diffusion, dielectric isolation diffusion, collector contact compensation diffusion, base diffusion (resistance diffusion), emitter diffusion (contact point), oxide film drilling (for electrodes) and wiring pattern processes; that is, it is necessary to repeat the mask formation seven times. In the manufacture of a MOS-IC or a planar transistor, it is necessary to repeat the mask formation at least four times. This will be described in detail with respect to the method of manufacturing a MOS transistor shown in FIG. 1, for example.
A thick SiO.sub.2 layer is formed on an entire surface of a p-type Si monocrystalline substrate 1 in accordance with the ordinary thermal oxidation method for the purpose of electrically isolating unit elements from each other, and is then subjected to etching so as to selectively remove the SiO.sub.2 layer leaving SiO.sub.2 regions 2 as shown in FIG. 1. Then, a gate insulating oxide film 3 is formed on the substrate surface portion between the SiO.sub.2 regions 2 by thermal oxidation, and a polycrystalline Si layer is formed over the entire surface by vapor growth. Furthermore, the Si layer is coated with a photosensitive agent, and is then partially subjected to a radiation such as light, electron beams or X-rays. Then, the polycrystalline Si layer is removed except the part of a gate 4, by etching. By employing this polycrystalline Si layer thus left as a mask, n-type impurities are introduced by diffusion or ion implantation, thereby to form a source region 5 and a drain region 6. Then, after a SiO.sub.2 film 7 is formed over the gate 4 as shown in FIG. 2, contact holes are formed by the lithography technique at regions of the source, the drain, and the gate metal layers 8 which will be employed as electrode material and wiring material are deposited by vacuum evaporation and the lithography technique as desired.
The above described method of manufacturing MOS transistors relates, in general to self-aligned silicon gate MOS transistors. This method is extensively employed for manufacturing transistors which are relatively small in area, because in the method the gate, source and drain regions are self-aligned. Substantially the same manufacturing method as that described above is employed for manufacturing other MOS transistors.
In the case of the above-described manufacturing method, as to the number of times of mask alignment, the mask formation must be repeated five or six times for the SiO.sub.2 film 2 for isolation, the gate 4, the contact holes of the source, the drain and the gate, a provision of the operation type, enhancement or depletion to the device, and the partially removal of the oxide film adapted to protect the surface after the metal film formation.
Due to the necessity of the frequent mask formations, the manufacturing process is necessarily intricate and the productivity is low. In addition, the errors in accuracy between the mask formations are accumulated, as a result of which it is necessary to have a larger margin in pattern design, which leads to an increase in area of the semiconductor device which preferably should be avoided.
Furthermore, in a method of employing the lithography technique with electron beams instead of using such a mask, direct exposure must be carried out several times. Accordingly, this method also suffers from the above-described disadvantages, and it is rather difficult to put this method in practical use because of the low accuracy and stability of the electron beam exposure device.